`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:22:17 03/30/2014 
// Design Name: 
// Module Name:    Three 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Three(speaker, clk); 
   
	input clk;    
	output speaker;    
	reg [22:0] tone;  
	reg [14:0] counter;  
	reg speaker;

	wire [6:0] ramp = (tone[22] ? tone[21:15] : ~tone[21:15]);    
	wire [14:0] clkdivider = {2'b01, ramp, 6'b000000}; 
	
	always @(posedge clk) tone <= tone+23'b1;      
		
	always @(posedge clk) 
		if(counter==0) counter <= clkdivider; 
		else counter <= counter-15'b1;    
			 
	always @(posedge clk) 
		if(counter==0) speaker <= ~speaker;    
   
endmodule  
